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readable-hls-generator - Generate and validate readable Vitis HLS

Creates, modifies, reviews, annotates, and validates readable AMD-Xilinx/Vitis HLS C/C++ kernels and related reports.

Tags

Updated: 2026-09-29

Capabilities

Typical Inputs

Typical Outputs

What this skill does

  • Generate readable HLS kernels
  • Modify HLS kernels
  • Review HLS artifacts
  • Annotate HLS code
  • Validate HLS artifacts
  • Run Vitis simulations
  • Request remote acceptance

Inputs

  • Confirmed HLS JSON spec
  • HLS behavior contract
  • HLS C/C++ artifacts
  • Vitis reports
  • Baseline artifact tree
  • Writable output directory
  • Remote server configuration
  • Readiness target

Outputs

  • HLS C/C++ headers
  • HLS C/C++ sources
  • C++ testbenches
  • .cfg files
  • Test vectors
  • Validation reports
  • Generated prompts
  • Validation JSON
  • Remote acceptance status
  • Dependency request files

Requirements

  • Python environment
  • Required skill dependencies
  • AMD-Xilinx Vitis tools
  • Configured remote Vitis server
  • Confirmed generation requirements

Source

  • Spec: SKILL.md

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HLS
Vitis HLS
AMD Xilinx
C++
FPGA
code generation
code review
hardware synthesis
verification
Generate readable HLS kernels
Modify HLS kernels
Review HLS artifacts
Annotate HLS code
Confirmed HLS JSON spec
HLS behavior contract
HLS C/C++ artifacts
HLS C/C++ headers
HLS C/C++ sources
C++ testbenches