testing-vlsi-verify-agentic - End-to-End Testing for VLSI Agentic Verification Pipeline
Tests the VLSI agentic verification CLI pipeline across APB, UART Lite, and LLM-backed demo flows.
Tags
Updated: 2026-09-23Capabilities
Typical Inputs
Typical Outputs
What this skill does
- Test VLSI CLI pipeline end-to-end
- Run APB example verification flow
- Extract simulator functional coverage reports
- Execute UART Lite demo workflow
- Audit LLM calls and artifacts
- Run pytest and ruff regressions
Inputs
- Markdown specification files
- RTL design source files
- Orchestrator configuration files
- OpenAI API key
- GitHub personal access token
Outputs
- Run state JSON files
- Functional coverage JSON reports
- Agent trace and LLM call logs
- Signoff package Markdown reports
- Generated testbench files
Requirements
- Python environment with dev dependencies
- Icarus Verilog toolchain
- Verilator simulator
- OpenAI API key for LLM-backed execution
- GitHub personal access token for GitHub operations