uvm - UVM Coding Convention and Methodology
UVM coding conventions and methodology guidelines based on IEEE 1800.2-2020 standard
Tags
Updated: 2026-06-30Capabilities
Typical Inputs
Typical Outputs
What this skill does
- write UVM testbenches
- build UVM environments
- create UVM components
- register components with factory
- implement TLM ports
- configure virtual interfaces
- integrate coverage
- define naming conventions
Inputs
- protocol specification
- module name
- virtual interface
- coverage requirements
Outputs
- UVM testbench files
- UVM environment components
- coverage reports
- verification results
Requirements
- IEEE 1800.2-2020 UVM Standard
- SystemVerilog environment
- UVM library
- Phase 5 verification