claude-skill-verilog - Verilog/SystemVerilog style and Verilator workflow guide
verilog systemverilog verilator yosys
★ 18 · Updated 2026-09-23
Provides coding style guidelines, Yosys compatibility rules, and Verilator linting and simulation workflows for Verilog and SystemVerilog.
⚙ Guide Verilog and SystemVerilog coding ⚙ Apply fixed-point Q notation rules ⚙ Separate combinational and sequential logic