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claude-skill-verilog - Verilog/SystemVerilog style and Verilator workflow guide

Provides coding style guidelines, Yosys compatibility rules, and Verilator linting and simulation workflows for Verilog and SystemVerilog.

Tags

Updated: 2026-09-23
verilogsystemverilogverilatoryosyshdlrtl

Capabilities

Guide Verilog and SystemVerilog codingApply fixed-point Q notation rulesSeparate combinational and sequential logicCheck Yosys synthesis compatibility

Typical Inputs

Verilog source files (.v, .vh)SystemVerilog source files (.sv, .svh)Testbench files

Typical Outputs

Verilator linting reportsSimulation binaries and FST waveformsSynthesizable RTL code

What this skill does

  • Guide Verilog and SystemVerilog coding
  • Apply fixed-point Q notation rules
  • Separate combinational and sequential logic
  • Check Yosys synthesis compatibility
  • Configure Verilator linting and simulation
  • Implement CDC and FSM patterns

Inputs

  • Verilog source files (.v, .vh)
  • SystemVerilog source files (.sv, .svh)
  • Testbench files

Outputs

  • Verilator linting reports
  • Simulation binaries and FST waveforms
  • Synthesizable RTL code

Requirements

  • Verilator toolchain
  • Yosys synthesis toolchain

Source

  • Spec: SKILL.md

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