logic-synthesis - RTL to Gate-Level Netlist Logic Synthesis
logic synthesis RTL gate-level netlist ASIC
★ 207 · Updated 2026-06-30
Performs logic synthesis from RTL to gate-level netlist, covering SDC constraint validation, compile and optimisation, netlist quality checks, and LEC equivalence verification.
⚙ validate SDC timing constraints ⚙ run compile exploration ⚙ execute final synthesis compile