logic-synthesis - RTL to Gate-Level Netlist Logic Synthesis
Performs logic synthesis from RTL to gate-level netlist, covering SDC constraint validation, compile and optimisation, netlist quality checks, and LEC equivalence verification.
Tags
Updated: 2026-06-30Capabilities
Typical Inputs
Typical Outputs
What this skill does
- validate SDC timing constraints
- run compile exploration
- execute final synthesis compile
- check netlist quality
- run LEC equivalence verification
- generate synthesis sign-off reports
- parse Yosys synthesis logs
- generate PD handoff package
Inputs
- RTL design files
- SDC constraint files
- PDK or technology library
- EDA synthesis tool (Yosys / Design Compiler / Genus / Fusion Compiler)
- synthesis knowledge base file
Outputs
- Validated SDC file
- Gate-level netlist (.v)
- Timing report (setup and hold)
- Area report
- Power report
- LEC equivalence report
- Netlist QC checklist
- PD handoff package
Requirements
- Bash execution environment
- File read and write access
- At least one EDA synthesis tool installed (Yosys / Design Compiler / Genus / Fusion Compiler)
- RTL source files available