★ 18 · Updated 2026-09-23
Provides coding style guidelines, Yosys compatibility rules, and Verilator linting and simulation workflows for Verilog and SystemVerilog.
Browse skills that share this tag.
★ 18 · Updated 2026-09-23
Provides coding style guidelines, Yosys compatibility rules, and Verilator linting and simulation workflows for Verilog and SystemVerilog.
★ 18 · Updated 2026-03-09
Generates schematics, netlists, or HDL from approved requirements for hardware projects