OpenClaw Skills & Use Case Index

ClawIndex is an ecosystem-driven index of OpenClaw skills and real-world use cases.

Index

Skills tagged: EDA

Browse skills that share this tag.

logic-synthesis - RTL to Gate-Level Netlist Logic Synthesis
logic synthesis RTL gate-level netlist ASIC
★ 160 · Updated 2026-06-30
Performs logic synthesis from RTL to gate-level netlist, covering SDC constraint validation, compile and optimisation, netlist quality checks, and LEC equivalence verification.
⚙ validate SDC timing constraints ⚙ run compile exploration ⚙ execute final synthesis compile
scientific-eda - Scientific Exploratory Data Analysis
scientific-data exploratory-data-analysis EDA data-visualization
★ 39 · Updated 2026-05-09
Defensive exploratory data analysis for scientific data formats
⚙ capture problem context ⚙ create session folder ⚙ record data shape